Conventional DRAMs all use a variant of the basic one-transistor cell. The cell contents are read by sensing the charge stored on the capacitor in the one-transistor cell. That is, the charge in the capacitor is released onto the bit line, thus changing its voltage and causing the sense amplifier on the bit line to latch to a "1" or a "0" depending on the absence or presence of a charge on the capacitor. Thus, it is critically important to design the DRAM cell with adequate capacitance in order to achieve sufficient signal size.
The latest efforts toward this end include approaches utilizing "trench" capacitors and other techniques which result in more capacitance per unit area and also more process complexity. Also, considerable pressure is being put on the development of extremely thin capacitor dielectrics, on the order of 85 to 100 angstroms thin, in order to increase the capacitance per unit area.
Recently, a number of "inverted" type of trench capacitor cells have been reported. The term "inverted" is used to indicate that the electrode inside of the trench serves as the storage node, and the substrate surrounding the trench serves as the plate electrode. These approaches allow higher density, better refresh capability and better immunity to soft errors. However, they still depend on sensing a finite, small quantity of stored charge on a bit line with considerably larger total capacitance.
For example, M. Sakamoto, et al. in "Buried Storage Electrode (BSE) Cell for Megabit DRAMs," Proceedings of IEDM, 1985, pp. 710-713 describe a one-transistor, one-capacitor metal-oxide-semiconductor (MOS) memory cell wherein a buried polysilicon electrode refilled into a capacitor trench and connected to a transfer MOSFET electrode serves to store the signal charge, while the heavily doped substrate of a p/p.sup.++ epitaxial wafer serves as the capacitor plate. A one-transistor DRAM cell where both the transistor and the capacitor are fabricated on the sidewalls of a deep trench is described by W. F. Richardson, et al. in "A Trench Transistor Cross-Point DRAM Cell," Proceedings of IEDM, 1985, pp. 714-717. The charge storage node in the capacitor is primarily oxide isolated, thereby minimizing charge loss due to junction leakage and ionizing radiation. Since the capacitor is entirely contained in a single trench geometry, the capacitor is self-isolated, and there are no possibilities of parasitic sidewall transistors.
Finally, N. Lu, et al. in "The SPT Cell--A New Substrate-Plate Trench Cell for DRAMs," Proceedings of IEDM, 1985, pp. 771-772 relate that this cell is also superior to previously reported trench cells because the storage device is inside the trench, and the transfer device is fabricated in an n well. The p-channel one-device cell is formed with a trench capacitor which extends from the planar surface through the well and epitaxial layer into the heavily doped substrate. A conducting strap connects the polysilicon inside the trench to the associated source/drain of the transfer device. The authors recognize that the cell contains a vertical parasitic FET device where the source is the surface diffusion connecting the storage node to the transfer device, the drain is the substrate and the gate is the polysilicon-filled trench. This p-channel device will always have its gate and source connected and will not conduct if the threshold is sufficiently negative, which was achieved by using an n-well bias greater than the maximum stored voltage and the introduction of a retrograde well.
However, these devices retain the disadvantages of one-transistor memory cells in that the capacitor charge must be released onto the bit line to read the contents of the cell, and as a consequence maximizing the capacitance is a major issue in designing the cell.
A DRAM cell was reported in 1970 by W. M. Regitz, et al. in "Three-Transistor-Cell 1024-Bit 500-ns MOS RAM," IEEE Journal of Solid-State Circuits, Vol. SC-5, No. 5, October 1970, pp. 181-186, in which the charge on the capacitor was not dumped onto the bit line when reading the contents of the cell. Rather, the capacitor also served as the gate of another transistor, and the contents of the cell were read by sensing whether this transistor was turned on or off. This cell concept overcomes the disadvantage described in the previous paragraph for the one-transistor cell. However, at the time that this cell was reported, it was necessary to fabricate all elements (transistor, capacitors, etc.) of the cell on the surface of the silicon substrate. The resulting size of the cell rendered it unattractive for use in products because its area was substantially larger than the area of one- transistor cells.